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AK8180D ms1306 - e - 01 oct - 2011 - 1 - features 3 C 3 C 4 configurable 10 lvcmos outputs translate lvpecl in put to lvcmos output single, dual and mixed voltage supply available on 2.5v and 3.3v clock output frequency up to 250mhz o utput - t o - output skew : 200ps max high - impedance output control enable to drive up to 20 series terminated clock lines operating temperature range: - 4 0 to +85 package: 32 - pin l qfp (pb free) pin compatible with mpc945 6 description the AK8180D is a member of akm lvcmos clock fanout buffer family designed for telecom, networking and computer applications , requiring a ra nge of clocks with high performance and low skew . the AK8180D distributes 10 buffered clocks co nfigured by pin - setting per bank . the 10 outputs can drive 10 terminated 50 ? clock lines. AK8180D are derived f r o m akm long - term - experienced clock devic e technology , and enable clock output to p erform low skew . the AK8180D is ava ilable in a 7mm x 7mm 32 - pin lqfp pa ckage. block diagram 2.5v, 3.3v lvcmos 1:10 clock fanout buffer AK8180D
AK8180D oct - 2011 ms1306 - e - 01 - 2 - pin d escription s 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 v d d b g n d q b 0 v d d b q b 1 g n d q b 2 v d d c qc 0 qc 3 gnd qc 2 vddc qc 1 gnd vddc gnd vdda qa 2 gnd qa 1 vdda qa 0 ak 8180 d d s e l c n c v d d p c l k p p c l k n d s e l a d s e l b g n d mr / oe package: 32 - pin lqfp (top view) pin no. pin name pin type pullup /down d escription 1 nc --- -- no internal connection 2 vdd -- -- power supply 3 pclkp in pd lvpecl differential clock inputs 4 pclkn in pu/pd 5 dsela in pd divide select i nput for output bank a 6 dselb in pd divide select i nput for output bank b 7 dselc in pd divide select i nput for output bank c 8, gnd -- -- ground 9 vddc -- -- power supply for output bank c 10 qc0 out -- clock output bank c 11 gnd -- -- ground 12 qc1 out -- clock output bank c (continued on next page )
AK8180D ms1306 - e - 01 oct - 2011 - 3 - pin no. pin name pin type pullup /down description 13 vddc -- -- power supply for output bank c 14 qc2 out -- clock output bank c 15 gnd -- -- ground 16 qc3 out -- clock output bank c 17 vddc -- -- power supply for output bank c 1 8 vddb -- -- power supply f or output bank b 1 9 qb2 out -- clock output bank b 20 gnd -- -- ground 21 qb1 out -- clock output bank b 22 vddb -- -- power supply for output bank b 23 qb0 out -- clock output bank b 24 gnd -- -- ground 25 vdda -- -- power supply for output bank a 26 qa2 out -- clock output bank a 27 gnd -- -- ground 28 qa1 out -- clock output bank a 29 vdda -- -- power supply for output bank a 30 qa0 out -- clock output bank a 31 gnd -- -- ground 32 oe mr/ in pd master reset an d output enable (output disable = high impedance) pu: pull up pd: pull down ordering information part number marking shipping packaging package temperature range AK8180D ak 81 80 d tape and reel 32 - pin lqfp - 4 0 to 85
AK8180D oct - 2011 ms1306 - e - 01 - 4 - absolute maximum rating o ver operating free - air temperature range unless otherwise noted (1) items s ymbol ratings unit s upply v oltage vdd - 0.3 to 4.6 v input voltage vin gnd - 0.3 to vdd+0.3 v input c urrent (any pins except supplies) i in 1 0 ma storage temperature tstg - 5 5 to 13 0 ? c note (1) stress beyond those listed under absolute m ax imum r atings may cause perman ent damage to the device. these are stress ratings only. f unctional operation of the device at these or any other conditions beyond those indicated under recommend ed operating conditions is not implied. exposure to absolute - maximum - rating conditions for extended periods may affect device reliability. electrical par ameters are guaranteed only over the recommended operating temperature range. this device is man ufactured on a cmos process, therefore, generically susceptible to damage by excessive static voltage. failure to observe proper handling and in stallation procedures can cause damage . akm recommends that this device is handled with appropriate precautions . recommended operation condition s parameter s ymbol conditions m in typ m ax unit operating t emperature ta - 4 0 85 ? c supply voltage (1) vdd vdd ? 5% 2.375 2.5 2.625 v 3. 135 3.3 3. 465 (1) power of 2.5v or 3.3v require s to be supplied from a single source. a decoupling capacitor of 0.1 ? f for power supply line should be locat ed close to each vdd pin. supported vdd supply voltage con figurations supply voltage configuration vdd vdda vddb vddc gnd 3.3 v 3.3 v 3.3 v 3.3 v 3.3 v 0 v 3.3 v and 2.5 v 3.3 v 3.3 v or 2.5 v 3.3 v or 2.5 v 3.3 v or 2.5 v 0 v 2.5 v 2.5 v 2.5 v 2.5 v 2.5 v 0 v general specification parameter s ymbol conditions m in typ m ax unit o utput termination voltage vtt vdd/2 v esd protection 1 mm machine model 200 v esd protection 2 hbm human body model 2000 v lat ch - up immunity lu 200 ma power dissipation capacitance p er output 10 pf input capacitance 4.0 pf esd sensitive device
AK8180D ms1306 - e - 01 oct - 2011 - 5 - power supply current <3.3v> vdd = 3.3v ? 5%, ta: - 40 to +85 parameter s ymbol conditions m in typ m ax unit full operation (1) idd1 cclk0=2 50mhz clk_sel=l 95 12 0 ma quiescent state ( 1 ) (2) idd2 1.6 2. 6 ma ( 1 ) the outputs have no loads. (2) all inputs are in default state by the internal pull up/down resis ters. dc characteristics <3.3v> all specifications at vdd =vdda=vddb=vddc= 3.3 v ? 5% , ta: - 4 0 to +85 , unless otherwise noted parameter symbol conditions min typ max unit high l evel i nput v oltage v ih lvcmos 2.0 vdd+0.3 v low l evel i nput v oltage v il lvcmo s - 0.3 0. 8 v peak - to - peak input voltage vpp lvpecl 250 mv common mode range (1 ) vcmr lcpecl 1.1 vdd - 0.6 v input c urrent (2 ) i l 1 vin= gnd or vdd 200 a high level o utput voltage v oh i oh = - 2 4 ma (3 ) 2.4 v low level o utput voltage v ol i o l = + 2 4 ma (3 ) i o l = + 12 ma 0. 55 0.30 v output impedance 14 - 17 ? (1) vcmr(dc) is the crosspoint of the differential input signal. functional operation is obtained when the crosspoint is within t he vcmr range and the input swing lies within the vpp(dc) specification. (2) i nput pull - up / pull down resisto rs influence input current. (3) the AK8180D is capable of driving 50 ? transmission lines of the incident edge. each output drives one 50 ? parallel terminated transmission line to a termination voltage of vtt . alternatively, the device drives up to two 50 ? series terminated transmission lines. (4) i dd q is the dc current consumption of the device with all outputs open and the input in its default state or open. ac characteristics <3.3v> ( 1 ) all specifications at vdd=vdda=vddb=vddc = 3.3v ? 5%, ta: - 40 to +85 , unless otherwise noted (continued on next page) parameter symbol conditions min typ max unit input f requency f in pin: pclkp/n 0 250 mhz input pulse width t pwin pin: pclkp/n 1.4 ns peak - to - peak input voltage vpp pin: pclkp/n 500 1000 mv common mode range (2 ) vcmr pin: pc lkp/n 1.3 vdd - 0.8 input rise/fall time (3 ) t rin ,t fout pin: pclkp/n 0.8 to 2.0v 1.0 ns output frequency f out pin: q0 - 11 0 250 mhz propagation delay t plh t phl pclk to any q 1.3 2.2 3.55 n s output disable time t plz , t phz 10 ns output enable time t pzl , t pzh 10 ns output - to - output skew t skpp within one bank any output, same output divider any output, any output divider 150 200 350 ps device - to - device skew t skd 2.25 ns output pulse skew (4 ) t sko 200 ps
AK8180D oct - 2011 ms1306 - e - 01 - 6 - (1) ac characteristics apply for parallel output termination of 50 ? to vtt . (2) the AK8180D is functional up to an input and output clock frequency of 350mhz and is characterized up to 250mhz. (3) vcmr(ac) is the crosspoint of the differential input signal. normal ac operation is obtained when the crosspoint is within the vcmr ra nge and the input swing lies within the vpp(ac) specification. violation of vcmr or vpp impacts t plh /phl and t skd . (4) violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, devi ce - to - device skew, input pulse w idth, output duty cycle and maximum frequency specifications . (5) output pulse skew t sko is the absolute difference of the propagation delay times : | t plh - t p hl |. output duty cycle is frequency dependent (= 0.5 ? t sko x fout). for example at fout = 125 m hz the output duty cycle limit is 50% ? 2.5%. power supply current < 2.5 v> vdd= 2.5 v ? 5%, ta: - 40 to +85 parameter s ymbol conditions m in typ m ax unit full operation (1) idd1 cclk0=2 50mhz clk_sel=l 71 9 5 ma quiescent state ( 1 ) (2) idd2 1.6 2.5 ma ( 1 ) the outputs have no loads. (2) all inputs are in default state by the internal pull up/down resisters. dc characteristics <2.5v> all speci fications at vdd=vdda=vddb=vddc= 2.5v ? 5%, ta: - 40 to +85 , unless otherwise noted parameter symbol conditions min typ max unit high l evel i nput v oltage v ih lvcmos 1.7 vdd+0.3 v low l evel i nput v oltage v il lvcmos - 0.3 0. 7 v peak - to - peak input voltage vpp lvpecl 250 mv common mode range (1 ) vcmr lvpecl 1. 1 vdd - 0.7 v input c urre nt ( ) i l 1 vin=gnd or vdd 200 a high level o utput voltage v oh i oh = - 15 ma ( ) 1.8 v low level o utput voltage v ol i o l = + 15 ma ( ) 0. 6 v output impedance 17 - 20 ? (1) vcmr(dc) is the crosspoint of the differential input signal. functional operation is o btained when the crosspoint is within the vcmr range and the input swing lies within the vpp(dc) specification. (2) input pull - up / pull down resistors influence input current. (3) the AK8180D is capable of driving 50 ? transmission lines of the incident edge. ea ch output drives one 50 ? parallel terminated transmission line to a termination voltage of vtt . alternatively, the device drives up to two 50 ? series terminated transmission lines. (4) i dd q is the dc current consumption of the device with all outputs open an d the input in its default state or open. paramete r symbol conditions min typ max unit output duty cycle dc out dc ref = 50% x1 output dc ref = 25 - 75% x1/2 output 45 47 50 50 55 53 % output rise/fall time t r , t f 0.55 to 2.4v 0.1 1.0 n s
AK8180D ms1306 - e - 01 oct - 2011 - 7 - ac characteristics <2.5v> ( 1 ) all specifications at vdd=vdda=vddb=vddc= 2.5 v ? 5%, ta: - 40 to +85 , unless otherwise noted (1) ac characteristics apply for parallel output termination of 50 ? to vtt . (2) the AK8180D is functional up to an input and output clock frequency of 350mhz and is characterized up to 250mhz. (3) violation of the 1.0 ns maximum input rise and fall tim e limit will affect the device propagation delay, device - to - device skew, input pulse width, output duty cycle and maximum frequency specifications. (4) output pulse skew t sko is the absolute difference of the propagation delay times:| t plh - t p hl |. outpu t duty cycle is frequency dependent (= 0.5 ? t sko x fout). for example at fout = 125 mhz the output duty cycle limit is 50% ? 2.5%. ac characteristics ( 1 ) (2) all specifications at vdd , vddb = 3.3v ? 5%, vdda, vddc=2.5v ? 5%, ta : - 40 to +85 , unless otherwise noted (1) ac characteristics apply for parallel output termination of 50 ? to vtt . (2) for all other ac specificati ons , refer to 2.5v and 3.3v tables according to the supply voltage of the output bank . (3) output pulse skew t sko is the absolute difference of the propagation delay times:| t plh - t p hl |. output duty cycle is frequency dependent (= 0.5 ? t sko x fout). fo r example at fout = 125 mhz the output duty cycle limit is 50% ? 2.5%. parameter symbol conditions min typ max unit input f requency (2 ) f in pin: p clk p/n 250 m hz input pulse width t pwin pin: p clk p/n 1.4 n s peak - to - peak input voltage vpp pin: pclkp/n 5 00 1000 mv common mode range (2 ) vcmr pin: pclkp/n 1.1 vdd - 0.7 input rise/fall time (3 ) t rin ,t fout pin: p clk p/n 0.8 to 2.0v 1.0 n s output frequency (2 ) f out dselx = 0 x1 output dselx = 1 x1/2 output 250 125 mhz propagation delay t plh t phl p clk p/n to any q 1.4 2.4 4.4 n s output disable time t plz , t phz 10 n s output enable time t pzl , t pzh 10 n s output - to - output skew t skpp within one bank any ou tput, same output div ider any output, any output div ider 150 200 350 p s device - to - device skew t skd 3.0 n s output pulse skew (4 ) t sko 200 p s output duty cycle dc out dc ref = 50% x 1 or 1/2 output 4 5 50 55 % output rise/fall time t r , t f 0.6 to 1.8 v 0.1 1.0 n s parameter symbol conditions min typ max unit propagation delay t plh t phl p clk to any q see 3.3v table n s output - to - output skew t skpp within one bank any output, same output div ider any output, any output div ider 15 0 25 0 350 ps device - to - device skew t skd 2.5 ns output pulse skew (3 ) t sko 25 0 ps output duty cycle dc out dc ref = 50% x1 or 1/2 output 45 50 55 %
AK8180D oct - 2011 ms1306 - e - 01 - 8 - figure 1 pclk/pclkn ac test reference figure 2 output transla tion time test reference figure 3 propagation delay test reference figure 4 output - to - output skew figure 5 output duty cycle (dc)
AK8180D ms1306 - e - 01 oct - 2011 - 9 - function table the following table shows the input s /output s clock state configured through the control pins . table 1 : control - pin - setting function t able control pin d efault 0 1 dsela 0 qa0 - 2 = refclk x 1 qa0 - 2 = refclk x 1/2 dselb 0 qb0 - 2 = refclk x 1 qb0 - 2 = refclk x 1/2 dselc 0 qc0 - 3 = refclk x 1 qc0 - 3 = refclk x 1/2 oe mr/ 0 output enabled internal reset. outputs disabled. (high impedance )
AK8180D oct - 2011 ms1306 - e - 01 - 10 - package information ? mechanical data : 32 - lead lqfp b 5 b 0 . 0 5 0 . 1 5 0 . 0 9 0 . 2 0 0 . 10 m 0 . 30 0 . 45 1 8 9 16 17 24 25 32 7 . 00 9 . 00 0 . 20 9 . 0 0 0 . 2 0 7 . 0 0 0 . 80 1 0 . 40 0 . 80 1 . 6 0 m a x 1 . 3 5 1 . 4 5 s s 0 . 10
AK8180D ms1306 - e - 01 oct - 2011 - 11 - ? marking a: #1 pin index b: part number c: d ate code (7 digits) akm and the logo - - are the brand of akm ic s and identify that akm continues to offer t he best choice for high performance mixed - signal solution under this brand. ? rohs complian ce all integrated circuits form asahi kasei m icrodevices corporation (akm) assembled in lead - free packages* are fully compliant with rohs. (*) rohs compliant pr oducts from akm are identified with pb free letter indication on product label posted on the anti - shield bag and boxes. a b c
AK8180D oct - 2011 ms1306 - e - 01 - 12 - important notice ? these products and th eir specifications are subject to change without notice. when you consider any use or application of these products, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of th e products. ? descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully respo nsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of th ese information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note 1) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very h igh standards of performance and reliability. note2) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure t o function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. ? it is the responsibility of the buyer or distributor of akm products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from th e use of said product in the absence of such notification.

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